The present invention relates to a data pulse receiver.
In a digital transmission system, a data signal, which is a serial binary signal having binary 1s and 0s represented respectively by the presence and absence of positive voltage, is transmitted. Since, in the transmission of the data signal, the pulse level thereof is lowered, it is necessary to detect and amplify the low level data pulses or regenerate data. A data pulse receiver is used for data regeneration and/or clock recovery from an incoming digital signal. It provides a data regenerating circuit for producing, from an incoming digital data signal, a data signal and also, to provide a clock recovery circuit, from the incoming digital signal, a clock signal which is used for timing purposes in processing the data signal.
With the advent of the dawn of the Information Highway and the explosion of telecommunications, the quantity and speed of data transmission continues to grow. In the telecommunications industry as well as in the computer industry, there exists a need to transmit large quantities of data from point to point, for example between memory and processors in multiple processor computers. The large number of data bits coupled with the large number of connections create an interconnect bottle-neck which requires large numbers of data drivers with their associated large amount of electrical power. One way that is employed to overcome this congestion difficulty is to multiplex large numbers of parallel bit streams up to higher rate serial bit streams, thus reducing the numbers of electrical connections that need to be made. The need for low power multiplex and demultiplex circuits capable of combining data signals at, say, 50 Mb/s up to, for example, 1 Gb/s has attracted a number of commercial integrated circuit vendors. Nevertheless, the computer and communications industry continues to search for lower power solutions.
A technique that has been employed with success to reduce the number of interconnections in a communications switching equipment is to employ a method known as a contactless back plane. Such a method permits point-to-multipoint and multipoint-to-point data transmission over a passive backplane without loss of signal integrity due to the multipoint connections. In this method, distribution of the multi gigabit-per-second serial data employs a form of ac coupling, of such small proportions, that the data information is contained in the data transitions. In such a methodology, the received data at the demultiplex circuit is considerably attenuated, signal levels of only 70 mV peak to peak, or less, are not uncommnon. Reliable reception of the data requires special techniques, including signal amplification, wide frequency bandwidth, matched input impedance and some form of hysteresis to discriminate against unwanted noise signals. The resultant signal is to be restored to a non-return-to-zero (NRZ) format from a return-to-zero (RZ) format.
U.S. Pat. No. 5,852,637, issued Dec. 22, 1998 and entitled xe2x80x9cA Serial Multi-Gb/s Data Receiverxe2x80x9d by A. K. D. Brown, et al. discloses a data pulse receiver which regenerates data in NRZ format from a return-to zero (RZ) format data signal. The data pulse receiver includes a data regenerator having a hysteresis circuit for regenerating data from an incoming data signal and a peak detector for monitoring the pulse level of the data signal and automatically controlling current flowing in the hysteresis circuit. Also, U.S. application Ser. No. 09/054,440 entitled xe2x80x9cMulti-Gb/s Data Pulse Receiverxe2x80x9d filed by A. K. D. Brown on Apr. 3, 1998 and U.S. application Ser. No. 09/071,117 entitled xe2x80x9cMethod And Apparatus For Performing DATA Pulse Detectionxe2x80x9d filed by A. K. D. Brown on May 4, 1998 disclose data pulse receivers which regenerate data in NRZ format from RZ format data signals, the data pulse receivers including Williamson couplers for transmitting data signals to data regenerators and peak detectors. In each of these data pulse receivers, the data regenerator and the peak detector includes similar circuits having a set-reset flip-flop (RS-FF) as a hysteresis circuit and a tail current circuit. The tail current is automatically adjusted in response to the peak level detected by the peak detector. A drawback of these data pulse detectors is not to provide a precise hysteresis control of the RS-FFs.
It is an object of the present invention to provide an improved data pulse receiver which meets the requirement to detect serial data at gigabit-per-second rates received over a transmission medium through which the signal levels have been substantially attenuated.
According to one aspect of the present invention, there is provided a data pulse receiver responsive to a clocked data signal having a continuous sequence of transitions, the data pulse receiver comprising: data regeneration means for providing a hysteresis to regenerate data in response to a first input signal derived from the clocked data signal; level detection means for detecting a signal level of a second input signal derived from the clocked data signal; and control means for adjusting the hysteresis of the data regeneration means in response to the signal level detected by the level detection means.
For example, the data regeneration means comprises: a first differential amplifier including first and second transistors, the bases of which are ac grounded; and first hysteresis means including third and fourth transistors, the bases of which are connected to the collectors of the first and second transistors, operating current of the first hysteresis means being provided by a first current circuit, the first hysteresis means operating in response to first differential input signals fed to the emitters of the first and second transistors, the first differential input signals being derived from the differential input signal. The level detection means comprises: a second differential amplifier including fifth and sixth transistors, the bases of which are ac grounded; and second hysteresis means including seventh and eighth transistors, the bases of which are connected to the collectors of the fifth and sixth transistors, operating current of the second hysteresis means being provided by a second current circuit, the second hysteresis means operating in response to second differential input signals fed to the emitters of the fifth and sixth transistors, the second differential input signals being derived from the differential input signal, the output of the second hysteresis means varying the currents of the first and second current circuits. The control means comprises adjust means for adjusting the currents of the first and second current circuits by comparing the output of the second hysteresis means to a reference voltage, so that the currents of the first and second current circuits are essentially equal.
The level detection means operates as a peak detector for detecting the peak of the differential input signal derived from the data signal. The differential input signals are provided to the data regeneration means and the level detection means via first and second input impedance networks, respectively, which are connected to differential input terminals. The input impedances of the input terminals are essentially equal (e.g., 50 xcexa9). The impedance of impedance elements of the second input impedance network is double of that of the first input impedance network and thus, signal attenuation of the latter is twice as large as that of the former. By using the same bias current, non-linear effects in the data regeneration means and the level detection means are cancelled. The first and second hysteresis means convert an RZ pulse waveform into an NRZ data waveform.